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1 multiphase pwm regulator for amd fusion? mobile cpus ISL6267 the ISL6267 is designed to be completely compliant with amd fusion? specifications. the ISL6267 controls two voltage regulators (vrs) with three integrated gate drivers. the first vr can be configured as 3-, 2-, or 1-phase vr, while the second output can be configured as 2- or 1-phase vr, providing maximum flexibility. the two vrs share the serial control bus to communicate with the cpu and ac hieve lower cost and smaller board area compared wi th two-chip solutions. the pwm modulator of ISL6267 is based on intersil?s r3 (robust ripple regulator) technology?. compared with the traditional multi-phase buck regulator, the r3 modulator commands variable switching frequency duri ng load transients, achieving faster transient response. with the same modulator, it naturally goes into pulse frequency modulation in light load conditions, which achieves higher light load efficiency and extends battery life. the ISL6267 has several other key features. both outputs support dcr current sensing with a single ntc thermistor for dcr temperature compensation or accurate resistor current sensing. both outputs come with remote voltage sense, adjustable switching frequency, current monitor, oc protection, independent power-good indicators, temperature monitors, and a common thermal alert. applications ? amd fusion cpu/gpu core power ? notebook computers features ? supports amd svi 1.0 serial data bus interface ? dual output controller with integrated drivers - core vr configurable 3-, 2-, 1-phase with two integrated drivers - northbridge vr configurable 2- or 1-phase with one integrated driver ? precision voltage regulation - 0.5% system accuracy over-temperature - 0v to 1.55v in 12.5mv steps - enhanced load line accuracy ? supports multiple current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? programmable 1-, 2- or 3-phase for the core output and 1- or 2-phase for the northbridge output ? adaptive body diode conduction time reduction ? superior noise immunity and transient response ? output current monitor and thermal monitor ? differential remote voltage sensing ? high efficiency across entire load range ? programmable +vid offset for both core and nb ? programmable switching frequency for both outputs ? excellent dynamic current balance between phases ? ocp/woc, ovp, pgood, and thermal monitor ? small footprint 48 ld 6x6 tqfn package ? pb-free (rohs compliant) core performance on ISL6267eval1z figure 1. efficiency vs load figure 2. v out vs load 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 55 i out (a) efficiency (%) v out core = 1.1v v in = 8v v in = 12v v in = 19v 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 0 5 10 15 20 25 30 35 40 45 50 55 i out (a) v out (a) v in = 8v v in = 12v v in = 19v v out core = 1.1v fn7801.0 january 31, 2011 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL6267 2 january 31, 2011 fn7801.0 simplified application circ uit for high power cpu core figure 3. typical application circuit using inductor dcr sensing boot_nb ug1_nb ph1_nb lg1_nb boot2 ug2 ph2 lg2 boot1 ug1 ph1 lg1 pwm3 ISL6267 isump isumn ph1 ph2 ph3 vo1 vo2 vo3 gnd pad vsen fb comp vw vsen fb comp vw vcore_sense fb_nb comp_nb vw_nb vsen_nb vnb_sense vin vccp rtn_nb pgood isen1 isen2 isen3 enable vcore ph2 isl6208 vo2 vo1 vin vo3 ph1 vin vin vo1 ph3 ph1 vin vnb vdd pwm2_nb isl6208 vnb1 nb_ph1 vnb2 nb_ph2 isen1_nb isen2_nb isump_nb isumn_nb nb_ph1 nb_ph2 vnb1 vnb2 rtn prog2 pwrok svd p svc ntc vr_hot thermal indicator prog1 pgood_nb ph1 ph2 ph3 nb_ph1 nb_ph2 ntc_nb fb2_nb
ISL6267 3 january 31, 2011 fn7801.0 simplified application circ uit for amd torpedo platform figure 4. typical application circuit using inductor dcr sensing boot_nb ug1_nb ph1_nb lg1_nb boot2 ug2 ph2 lg2 boot1 ug1 ph1 lg1 pwm3 ISL6267 isump isumn ph1 ph2 vo1 vo2 gnd pad vsen comp vw vsen comp vw vcore_sense fb_nb comp_nb vw_nb vsen_nb vnb_sense vin vccp rtn_nb pgood isen1 isen2 enable ph1 ph2 vcore ph2 vo2 vo1 ph1 vin vin vo1 ph1 vin vnb vdd pwm2_nb isl6208 vnb1 nb_ph1 vnb2 nb_ph2 isen1_nb isen2_nb nb_ph1 nb_ph2 isump_nb isumn_nb nb_ph1 nb_ph2 vnb1 vnb2 rtn vin +5v prog2 ntc pwrok svd p svc vr_hot thermal indicator prog1 pgood_nb ntc_nb fb2_nb isen3/fb2 fb
ISL6267 4 january 31, 2011 fn7801.0 simplified application circuit for low power cpu core and nb figure 5. typical application circuit using inductor dcr sensing boot_nb ug1_nb ph1_nb lg1_nb boot2 ug2 ph2 lg2 pgnd2 boot1 ug1 ph1 lg1 pwm3 ISL6267 isump isumn ph1 vo1 gnd pad vsen fb comp vw vsen fb comp vw vcore_sense fb_nb comp_nb vw_nb vsen_nb vnb_sense vin vccp rtn_nb pgood isen1 isen2 isen3 enable vcore vo1 ph1 vin vo1 ph1 vin vnb vdd pwm2_nb vnb1 nb_ph1 isen1_nb isen2_nb isump_nb isumn_nb nb_ph1 vnb1 rtn +5v +5v open +5v open prog1 open open open open open ntc vr_hot thermal indicator pwrok svd p svc prog2 pgood_nb open ntc_nb open optional optional
ISL6267 5 january 31, 2011 fn7801.0 simplified application circuit showing resistor sensing figure 6. typical application circuit using inductor dcr sensing boot_nb ug1_nb ph1_nb lg1_nb boot2 ug2 ph2 lg2 pgnd2 boot1 ug1 ph1 lg1 pwm3 ISL6267 isump isumn vop von gnd pad vsen fb comp vw vsen fb comp vw vcore_sense fb_nb comp_nb vw_nb vsen_nb vnb_sense vin vccp rtn_nb pgood isen1 isen2 isen3 enable vcore vin von vin vnb vdd pwm2_nb nb_n nb_p isen1_nb isen2_nb isump_nb isumn_nb nb_p nb_n rtn +5v +5v open +5v open prog1 open open open open open ntc vr_hot thermal indicator pwrok svd p svc prog2 pgood_nb open ntc_nb open vop optional optional
ISL6267 6 january 31, 2011 fn7801.0 block diagram svd svc pwrok boot_nb ug_nb ph_nb lg_nb pwm2_nb rtn_nb vsen_nb vw_nb comp_nb isump_nb isumn_nb d/a dac2 sleep dac1 prog1 vw fb rtn e/a - + + + comp isump isumn current sense phase current balance isen1 isen2 isen3/fb2 ov protection pwm3 boot1 ug1 ph1 lg1 vccp boot2 ug2 ph2 lg2 ibal pgood modulator vsen vin vdd enable d/a dac2 dac1 - + - + + + dac1 s - + current sense oc and woc protection phase current balance isen1 isen2 isen3/fb2 pwm3 boot1 ug1 ph1 lg1 boot1 ug1 ph1 lg1 boot2 ug2 ph2 lg2 boot2 ug2 ph2 lg2 ibal pgood driver driver driver driver fb2_nb mode (psi_l) isen2_nb isen1_nb northbridge (similar architecture to core section) controller and driver offset voltage prog2 vcore vnb a/d vid serial interface temp monitor t_monitor ntc vr_hot prog1 pgood_nb prog2 ntc_nb fb_nb
ISL6267 7 january 31, 2011 fn7801.0 pin configuration ISL6267 (48 ld qfn) top view 1 48 gnd pad (bottom) v s e n _ n b fb2_nb 2 fb_nb 3 comp_nb 4 vw_nb 5 6 pgood_nb 7 svd 8 pwrok 9 svc 10 enable 11 vr_hot 12 ntc 47 r t n _ n b 46 i s u m p _ n b 45 i s u m n _ n b 44 n t c _ n b 43 p r o g 2 42 41 40 b o o t 1 _ n b 39 u g 1 _ n b 38 p h 1 _ n b 37 l g 1 _ n b 36 pwm2_nb 35 boot2 34 ug2 33 ph2 32 lg2 31 vccp 30 pwm3 29 lg1 28 ph1 27 ug1 26 boot1 25 prog1 1 3 c o m p 1 4 f b 1 5 i s e n 3 / f b 2 1 6 i s e n 2 1 7 i s e n 1 1 8 v s e n 1 9 2 0 r t n 2 1 i s u m n 2 2 i s u m p 2 3 v d d 37 2 4 pgood v w i s e n 2 _ n b i s e n 1 _ n b v i n pin descriptions pin number symbol description 1 fb2_nb the components connecting to fb2_nb are used to adjust the compen sation in 1-phase mode to achieve optimum performance. 2 fb_nb output voltage feedback to the inverting input of the northbridge controller error amplifier. 3comp_nbnorthbridge vr error amplifier output. 4 vw_nb window voltage set pin used to set the switching frequency for the northbridge controller. a resistor from this pin to comp_nb programs the switching frequency (8k gives approximately 300khz). 5 pgood_nb open-drain output to indicate the northbridge port ion of the ic is ready to supply regulated voltage. pull- up externally to vccp or 3.3v. 6 svd serial vid data bi-directional signal from the cpu processor master device to the vr. 7 pwrok system power good input. when this pin is high, the svi interface is active and the i 2 c protocol is running. while this pin is low, the svc and svd input states determine the pre-pwrok metal vid. this pin must be low prior to the ISL6267 pgood output goin g high per the amd svi controller guidelines. 8svc serial vid clock input from the cpu processor master device. 9 enable enable input. a high level lo gic on this pin enables both vrs. 10 pgood open-drain output to indicate the core portion of the ic is ready to supply regulated voltage. pull up externally to vccp or 3.3v. 11 vr_hot thermal overload open drain output indicator active low. 12 ntc thermistor input to vr_hot circuit to monitor core vr temperature. 13 vw window voltage set pin used to set the switching fr equency for the core controll er. a resistor from this pin to comp programs the switching frequency (8k gives approximately 300khz). 14 comp error amplifier output. 15 fb output voltage feedback to the inverting input of the core controller error amplifier.
ISL6267 8 january 31, 2011 fn7801.0 16 isen3/fb2 when the core vr of ISL6267 is configured in 3- phase mode, this pin is isen 3. isen3 is the individual current sensing for channel 3. when the core vr of ISL6267 is configured in 2- phase mode, this pin is fb2. there is a switch between the fb2 pin and the fb pin. the switch is on in 2-phase mode and is off in 1-phase mode. the components connecting to fb2 are used to adjust the compensation in 1-phase mode to achieve optimum performance. 17 isen2 individual current sensing for channel 2 of the core vr. when isen2 is pulled to 5v vdd, the controller disables channel 2, and the core vr runs in single-phase mode. 18 isen1 individual current sensing for channel 1 of the core output. 19 vsen output voltage sense pin for the core controller. connect to the +sense pin of the microprocessor die. 20 rtn output voltage sense return pin for the core contro ller. connect to the -sense pin of the microprocessor die. 21 isumn inverting input of the transconductance amplifie r for current monitor and load line of core output. 22 isump non-inverting input of the transconductance amplif ier for current monitor and load line of core output. 23 vdd 5v bias power. 24 vin battery supply voltage, used for feed-forward. 25 prog1 program pin for setting output voltage offset for core vr. 26 boot1 connect an mlcc capacitor across the boot1 and the phase (ph1) pin. the boot capacitor is charged through an internal boot diode connected from the vccp pin to the boot1 pin, each time the ph1 pin drops below vccp minus the voltage dropped across the internal boot diode. 27 ug1 output of the phase 1 high-side mosfet gate driver of the core vr. connect the ug1 pin to the gate of the phase 1 high-side mosfet. 28 ph1 current return path for the phase 1 high-side mosfet gate driver of vr1. connect the ph1 pin to the node consisting of the high-side mosfet source, the low-side mosfet drain, and the output inductor of phase 1. 29 lg1 output of the phase 1 low-side mosfet gate driver of the core vr. connect the lg1 pin to the gate of the phase 1 low-side mosfet. 30 pwm3 pwm output for channel 3 of the core vr. when pwm3 is pulled to 5v vdd, the controller disables phase 3 and runs in 2-phase mode. 31 vccp input voltage bias for the internal gate drivers. co nnect +5v to the vccp pin. decouple with at least 1f of capacitance to gnd. a high quality, x7r dielectric mlcc capacitor is recommended. 32 lg2 output of the phase 2 low-side mosfet gate driv er of vr1. connect the lg2 pin to the gate of the phase 2 low-side mosfet. 33 ph2 current return path for the phase 2 high-side mosfet gate driver of the core vr. connect the ph2 pin to the node consisting of the high-sid e mosfet source, the low-side mosfet drain, and the output inductor of phase 2. 34 ug2 output of the phase 2 high-side mosfet gate driver of the core vr. connect the ug2 pin to the gate of the phase 2 high-side mosfet. 35 boot2 connect an mlcc capacitor across the boot2 and ph2 pins. the boot capacitor is charged through an internal boot diode connected from the vccp pin to the boot2 pin, each time the ph2 pin drops below vccp minus the voltage dropped across the internal boot diode. 36 pwm2_nb pwm output for channel 2 of the northbridge vr. 37 lg1_nb output of the low-side mosfet gate driver of th e northbridge vr. connect the lg1_nb pin to the gate of the low-side mosfet of vr2. 38 ph1_nb current return path for the high-side mosfet gate driver of the northbridge vr. connect the ph1_nb pin to the node consisting of the hi gh-side mosfet source, the low-side mosfet drain, and the output inductor of the northbridge vr. 39 ug1_nb output of the high-side mosfet gate driver of the northbridge vr. connect the ug1_nb pin to the gate of the high-side mosfet. pin descriptions (continued) pin number symbol description
ISL6267 9 january 31, 2011 fn7801.0 40 boot1_nb connect an mlcc capacitor across the boot1_nb and the ph1_nb pins. the boot capacitor is charged through an internal boot diode connected from the vccp pin to the boot1_nb pin, each time the ph1_nb pin drops below vccp minus the voltage dropped across the internal boot diode. 41 prog2 program pin for setting output voltage offset for northbridge vr. 42 ntc_nb thermistor input to vr_hot circui t to monitor northbridge vr temperature. 43 isumn_nb inverting input of the transconductance amplifier for current monitor and load line of the northbridge vr. 44 isump_nb non-inverting input of the transconductance amplifier for current monitor and load line of the northbridge vr. 45 rtn_nb output voltage sense return pin for the northb ridge controller. connect to the -sense pin of the microprocessor die. 46 vsen_nb output voltage sense pin for the northbridge cont roller. connect to the +sense pin of the microprocessor die. 47 isen2_nb individual current sensing for channel 2 of the northbridge vr. when isen2 is pulled to 5v vdd, the controller will disable channel 2 and the northbridge vr will run single-phase. 48 isen1_nb individual current sensing for channel 1 of the northbridge vr. gnd (bottom pad) signal common of the ic. unless otherwise stated, signals are referenced to the gnd pin. pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6267hrz ISL6267 hrz -10 to +100 48 ld 6x6 qfn l48.6x6b ISL6267eval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% m atte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL6267 . for more information on msl please see tech brief tb363 .
ISL6267 10 january 31, 2011 fn7801.0 table of contents core performance on ISL6267eval1z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 simplified application circuit for high power cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 simplified application circuit for amd torpedo platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 simplified application circuit for low power cpu core and nb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 simplified application circuit showing resistor sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 gate driver timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 multiphase r3? modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 diode emulation and period stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 serial vid interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pre-pwrok metal vid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 vfix mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 svi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 vid-on-the-fly transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 svi wire protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 svi bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 vr offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 voltage regulation and load line implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 differential sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 phase current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 ccm switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 dynamic operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 fb2 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 adaptive body diode conduction time reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 key component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 inductor dcr current-sensing network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 resistor current-sensing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 overcurrent protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 load line slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 compensator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 ntc thermal monitors and vr_hot function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ISL6267 11 january 31, 2011 fn7801.0 absolute maximum rating s thermal information supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v battery voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase) . . . . . . . . . . . . . . . . -0.3v to +7v(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +9v(<10ns) phase voltage (phase) . . . . . . . . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . .phase - 0.3v (dc) to bootphase - 5v . . . . . . . . . . . . . . . . . (<20ns pulse width, 10j) to boot lgate voltage . . . . . . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd + 0.3v) open drain outputs, pgood, vr_hot. . . . . . . . . . . . . . . . . . . -0.3v to +7v thermal resistance (typical) ja (c/w) jc (c/w) 48 ld qfn package (notes 4, 5) . . . . . . . . 28 1 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to 25v ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operatin g temperature range, -10c to +100c. parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vdd enable = 1v 9 10.5 ma enable = 0v 1 a battery supply current i vin enable = 0v 1 a v in input resistance r vin enable = 1v 550 k power-on-reset thresholds vdd por threshold vdd_por r v dd rising 4.35 4.5 v vdd_por f v dd falling 4.00 4.15 v vin por threshold vin_por r v in rising 4.00 4.35 v vin_por f v in falling 2.8 3.30 v system and references system accuracy hrz %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.55v -0.5 +0.5 % vid = 0.50v to 0.7375v -8 +8 mv vid = 0.25v to 0.4875v -15 +15 mv maximum output voltage v cc_core(max) vid = [0000000] 1.55 v minimum output voltage v cc_core(min) vid = [1111111] 0.0 v channel frequency nominal channel frequency f sw(nom) 280 300 320 khz adjustment range 200 500 khz amplifiers current-sense amplifier input offset i fb = 0a -0.15 +0.15 mv error amp dc gain a v0 90 db error amp gain-bandwidth product gbw c l = 20pf 18 mhz
ISL6267 12 january 31, 2011 fn7801.0 isen imbalance voltage maximum of isens - minimum of isens 1 mv input bias current 20 na power-good and protection monitors pgood low voltage v ol i pgood = 4ma 0.26 0.4 v pgood leakage current i oh pgood = 3.3v -1 1 a pgood delay t pgd 460 s gate driver ugate pull-up resistance r ugpu 200ma source current 1.0 1.5 ugate source current i ugsrc ugate - phase = 2.5v 2.0 a ugate sink resistance r ugpd 250ma sink current 1.0 1.5 ugate sink current i ugsnk ugate - phase = 2.5v 2.0 a lgate pull-up resistance r lgpu 250ma source current 1.0 1.5 lgate source current i lgsrc lgate - vssp = 2.5v 2.0 a lgate sink resistance r lgpd 250ma sink current 0.5 0.9 lgate sink current i lgsnk lgate - vssp = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 23 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 28 ns bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma 0.58 v reverse leakage i r v r = 25v 0.2 a protection overvoltage threshold ov h vsen rising above setpoint for >1ms 200 270 330 mv severe overvoltage threshold ov hs v o rising above threshold > 0.5s 1.800 v undervoltage threshold ov h vsen falls below setpoint for >1ms 260 330 400 mv current imbalance threshold one isen above another isen for >1.2ms 9 mv core ocp current threshold 3-phase ccm, 2-phase ccm, 1-phase 50 60 70 a 3-phase de 16 20 24 a 2-phase de 24 30 36 a northbridge ocp current thre shold 2-phase ccm, 1-phase 50 60 70 a 2-phase de 24 30 36 a logic thresholds enable input low v il 0.3 v enable input high v ih 0.7 v pwm pwm output low v 0l sinking 5ma 1.0 v pwm output high v 0h sourcing 5ma 3.5 v pwm tri-state leakage pwm = 2.5v 2 a thermal monitor ntc source current ntc = 1.3v 57 67 a ntc_nb source current ntc_nb = 1.3v 57 67 a thermal monitor trip voltage falling threshold 0.87 0.88 0.89 v thermal monitor reset voltage rising threshold 0.91 0.92 0.93 v electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operatin g temperature range, -10c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL6267 13 january 31, 2011 fn7801.0 gate driver timing diagram inputs enable leakage current i enable en = 0v -1 0a en = 1v 18 36 a slew rate (for vid change) sr 5 7.5 10 mv/s soft-start slew rate ssr 1.25 1.875 2.5 mv/s svi interface pwrok, svc, svd input logic high v ih 0.798 -v pwrok, svc, svd input logic low v il - - 0.57 v svc, svd leakage en = 0v, svc and svd = 0v - -1a en = 5v, svc and svd = 1.8v - - 1 a note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c, f sw = 300khz, unless otherwise noted. boldface limits apply over the operatin g temperature range, -10c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr
ISL6267 14 january 31, 2011 fn7801.0 theory of operation multiphase r 3 ? modulator the ISL6267 is a multiphase regulator implementing two voltage regulators, vdd and vddnb, on one chip controlled by amd?s? svi1? protocol. vdd can be programmed for 1-, 2- or 3-phase operation. vddnb can be configured for 1- or 2-phase operation. both regulators use the intersil patented r 3 ? (robust ripple regulator) modulator. the r 3 ? modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their shortcomings. figure 7 conceptually shows the multiphase r 3 ? modulator circuit, and figure 8 shows the operation principles. a current source flows from the vw pin to the comp pin, creating a voltage window set by the resistor between the two pins. this voltage window is called ?vw window? in the following discussion. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuits. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one-shot master clock signal. a phase sequencer distributes the master clock signal to the slave circuits. if v dd is in 3-phase mode, the master clock signal is distributed to the three phases, and the clock 1~3 signals will be 120 out-of-phase. if vr1 is in 2-phase mode, the master clock signal is distributed to phases 1 and 2, and the clock1 and clock2 signals will be 180 out-of- phase. if vr1 is in 1-phase mode, the master clock signal will be distributed to phase 1 only and be the clock1 signal. each slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs voltage v crs hits vw, the slave circuit turns off the pwm pulse, and the current source discharges c rs . since the controller works with v crs , which are large amplitude and noise-free synthesized signals, it achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the error amplifier allows the isl6 267 to maintain a 0.5% output voltage accuracy. figure 9 shows the operation principles during load insertion response. the comp voltage ri ses during load insertion, generating the master clock sign al more quickly, so the pwm pulses turn on earlier, increasing the effective switching frequency. this allows for higher control loop bandwidth than conventional fixed frequency pwm controllers. the vw voltage rises as the comp voltage rises, making the pwm pulses wider. during load release response, th e comp voltage falls. it takes the master clock circuit longer to generate the next master clock signal so the pwm pulse is held off until needed. the vw voltage falls as the comp voltage falls, reducing the current pwm pulse width. this kind of behavior gi ves the ISL6267 ex cellent response speed. the fact that all the phases share the same vw window voltage also ensures excellent dynamic current balance among phases. figure 7. r 3 ? modulator circuit crm gmvo master clock vw comp master clock phase sequencer clock1 clock2 r i l1 gm clock1 phase1 crs1 vw s q pwm1 l1 r i l2 gm clock2 phase2 crs2 vw s q pwm2 l2 co vo vcrm vcrs1 vcrs2 master clock circuit slave circuit 1 slave circuit 2 r i l3 gm clock3 phase3 crs3 vw s q pwm3 l3 vcrs3 slave circuit 3 clock3 figure 8. r 3 ? modulator operation principles in steady state comp vcrm master clock pwm1 vw clock1 pwm2 clock2 hysteretic window pwm3 vcrs3 clock3 vcrs2 vcrs1 vw
ISL6267 15 january 31, 2011 fn7801.0 diode emulation and period stretching the ISL6267 can operate in di ode emulation (de) mode to improve light-load efficiency. in de mode, the low-side mosfet conducts when the current is flowing from source to drain and does not allow reverse current, th us emulating a diode. as figure 10 shows, when lgate is on, the low-side mosfet carries current, creating negative voltage on th e phase node due to the voltage drop across the on-resistance. the ISL6267 monitors the current by monitoring the phase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. if the load current is light enough, as figure 10 shows, the inductor current reaches and stays at zero before the next phase node pulse, and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reaches 0a, and the regulator is in ccm, although the controller is in de mode. figure 11 shows the operation principle in diode emulation mode at light load. the load gets increm entally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size and therefore is the same, making the inductor current triangle the same in the three cases. the ISL6267 clamps the ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v crs , naturally stretching the switching period. the inductor current triangles move farther apart su ch that the inductor current average value is equal to the load current. the reduced switching frequency helps increase light-load efficiency. start-up timing with the controller's v dd and v in voltages above their por threshold, the start-up sequence begins when enable exceeds the logic high threshold. figure 12 shows the typical start-up timing of vr1 and vr2. the ISL6267 uses digital soft-start to ramp-up dac to the voltage programmed by the metal vid. pgood is asserted high and low at the end of the ramp up. similar results occur if enable is tied to v dd , with the soft-start sequence starting 800s after v dd crosses the por threshold. figure 9. r 3 ? modulator operation principles in load insertion response comp v crm master clock pwm1 vcrs1 vw clock1 pwm2 vcrs2 clock2 pwm3 clock3 vcrs3 vw ugate phase il lgate figure 10. diode emulation il il v crs il v crs v crs vw ccm / dcm boundary light dcm deep dcm vw vw figure 11. period stretching
ISL6267 16 january 31, 2011 fn7801.0 power-on reset before the controller has suffic ient bias to guarantee proper operation, the ISL6267 requires bo th a +5v input supply tied to v cc and pv cc , as well as a battery or other input supply tied to v in , to exceed their respective rising power-on reset (por) thresholds. once these thresholds are reached or exceeded, the ISL6267 has enough bias to begin checking svi inputs. hysteresis between the rising an d the falling thresholds assure the ISL6267 does not inadverten tly turn off unless the bias voltage drops substantially (see ?electrical specifications? on page 11). serial vid interface the on-board serial vid interf ace (svi) circuitry allows the processor to directly control th e core and northbridge voltage reference levels within the ISL6267. the svc and svd states are decoded according to the pwrok inputs as described in the following sections. the ISL6267 uses a digital-to-analog converter (dac) to generate a reference voltage based on the decoded svi value. see figure 13 for a simple svi interface timing diagram. pre-pwrok metal vid typical motherboard start-up begi ns with the controller decoding the svc and svd inputs to determine the pre-pwrok metal vid setting (see table 1). once the enable input exceeds the rising threshold, the ISL6267 decodes an d locks the decoded value in an on-board hold register. vdd enable dac 800s 1.875mv/s metalvid slew rate vid command voltage pgood pwrok vin figure 12. typical soft-start waveforms vcc svc svd enable pwrok v core / v nb 1 7 89 10 11 12 figure 13. svi interface timing diagra m: typical pre-pwrok metal vid start-up pgood 3 4 2 5 6 metal_vid metal_vid v_svi v_svi interval 1 to 2: ISL6267 waits to por. interval 2 to 3: svc and svd are externally set to pre-metal vid code. interval 3 to 4: enable locks pre-metal vid code. all outputs soft-start to this level. interval 4 to 5: pgood signal goes high, indicating proper operation. interval 6 to 7: svc and svd data lines communicate change in vid code. interval 7 to 8: ISL6267 responds to vid-on-the-fly code change. interval 8 to 9: pwrok is driven low, and isl6 267 returns all outputs to pre-pwrok metal vid level. interval 9 to 10: pwrok driven high once again by cpu, and ISL6267 prepares for svi commands. interval 10 to 11: svc and svd data lines communicate new vid code. interval 11 to 12: ISL6267 driv es outputs to new vid code level. interval 5 to 6: cpu detects pgood high, and drives pwrok high, to allow ISL6267 to prepare for svi commands. post 12: enable falls, all internal drivers are tri-stat ed, and pgood is driven low.
ISL6267 17 january 31, 2011 fn7801.0 the internal dac circuitry begins to ramp core and northbridge vrs to the decoded pre-pwrok metal vid output level. the digital soft-start circuitry ramps the internal reference to the target gradually at a fixed rate of approximately 2mv/s. the controlled ramp of all output voltage planes reduces in-rush current during the soft-start interval. at the end of the soft-start interval, the pgood output transiti ons high, indicating all output planes are within regulation limits. if the enable input falls below the enable falling threshold, the ISL6267 tri-states both outputs. pgood is pulled low with the loss of enable. the core and northbridge planes decay, based on output capacitance and load leakage resistance. if bias to vcc falls below the por level, the ISL6267 responds in the manner previously described. once vcc and enable rise above their respective rising thresholds, the internal dac circuitry re- acquires a pre-pwrok metal vi d code, and the controller soft-starts. vfix mode the ISL6267 does not support vfix mode. in the event a cpu is not present on a motherboard and the ISL6267 is powered on, the state of svc and svd sets the pre-pwrok metal vid as the ?pre-pwrok metal vid? on page 16 and begins soft-starting. svi mode once the controller has successfully soft-starts and pgood and pgood_nb transition high, the processor can assert pwrok to signal the ISL6267 to prepare for svi commands. the controller actively monitors the svi interface for set vid commands to move the plane voltages to start-up vid values. details of the svi bus protocol are provided in th e ?amd design guide for voltage regulator controllers accepting serial vid codes? specification. once a set vid command is received, the ISL6267 decodes the information to determine which vr is affected and which vid target is required (see table 2). the internal dac circuitry steps the output voltage of the vr commanded to the new vid level. during this time, one or more of the vr outputs could be targeted. in the event either vr is commanded to power-off by serial vid commands, the pgood signal remains asserted. if the pwrok input is de-asserted , then the controller steps both the core and the northbridge vrs back to the stored pre-pwrok metal vid level in the holding register from initial soft-start. no attempt is made to read the svc and svd inputs during this time. if pwrok is re-asserted, then the on-board svi interface waits for a set vid command. if enable goes low during normal operation, all internal drivers are tri-stated and pgood is pulled low. this event clears the pre-pwrok metal vid code and forces the controller to check svc and svd upon restart. a por event on either vcc or vi n during normal operation shuts down both regulators, and both pgood outputs are pulled low. the pre-pwrok metal vid code is not retained. vid-on-the-fly transition once pwrok is high, the ISL6267 detects this flag and begins monitoring the svc and svd pins for svi instructions. the microprocessor follows the protoc ol outlined in the following sections to send instructions for vid-on-the-fly transitions. the ISL6267 decodes the in struction and acknowledges the new vid code. for vid codes higher than the current vid level, the ISL6267 begins steppi ng the commanded vr outputs to the new vid target with a typical slew rate of 7.5mv/s, which meets the amd requirements. when the vid codes are lower than the current vid level, the ISL6267 checks the state of psi_l. if psi_l is high, the controller begins stepping the regulator output to the new vid target with a typical slew rate of -7.5mv/s. if psi_l is low, the controller allows the output voltage to decay and slowly steps the dac down with the natural decay of the output. this allows the controller to quickly recover and move to a high vid code if commanded. amd requirements under these conditions do not require the regulator to meet the minimum slew rate specification of -5mv/s. in eith er case, the slew rate is not allowed to exceed 10mv/s. the ISL6267 does not change the state of pgood (vccpwrgd in amd specifications) when a vid-on-the-fly transition occurs. svi wire protocol the svi wire protocol is based on the i 2 c bus concept. two wires [serial clock (svc) and serial data (svd)], carry information between the amd processor (master) and vr controller (slave) on the bus. the master initiates and terminates svi transactions and drives the clock, svc, during a transaction. the amd processor is always the master, and the voltage regulators are the slaves. the slave receives the svi transactions and acts accordingly. mobile svi wire protocol timing is based on high-speed mode i 2 c. see amd publication # 40182 for additional details. table 1. pre-pwrok metal vid codes svc svd output voltage (v) 00 1.1 01 1.0 10 0.9 11 0.8
ISL6267 18 january 31, 2011 fn7801.0 . table 2. serial vid codes svid[6:0] voltage (v) svid[6:0] voltage (v) svid[6:0] voltage (v) svid[6:0] voltage (v) 000_0000b 1.5500 010_0000b 1.1500 100_0000b 0.7500 110_0000b 0.3500 * 000_0001b 1.5375 010_0001b 1.1375 100_0001b 0.7375 110_0001b 0.3375 * 000_0010b 1.5250 010_0010b 1.1250 100_0010b 0.7250 110_0010b 0.3250 * 000_0011b 1.5125 010_0011b 1.1125 100_0011b 0.7125 110_0011b 0.3125 * 000_0100b 1.5000 010_0100b 1.1000 100_0100b 0.7000 110_0100b 0.3000 * 000_0101b 1.4875 010_0101b 1.0875 100_0101b 0.6875 110_0101b 0.2875 * 000_0110b 1.4750 010_0110b 1.0750 100_0110b 0.6750 110_0110b 0.2750 * 000_0111b 1.4625 010_0111b 1.0625 100_0111b 0.6625 110_0111b 0.2625 * 000_1000b 1.4500 010_1000b 1.0500 100_1000b 0.6500 110_1000b 0.2500 * 000_1001b 1.4375 010_1001b 1.0375 100_1001b 0.6375 110_1001b 0.2375 * 000_1010b 1.4250 010_1010b 1.0250 100_1010b 0.6250 110_1010b 0.2250 * 000_1011b 1.4125 010_1011b 1.0125 100_1011b 0.6125 110_1011b 0.2125 * 000_1100b 1.4000 010_1100b 1.0000 100_1100b 0.6000 110_1100b 0.2000 * 000_1101b 1.3875 010_1101b 0.9875 100_1101b 0.5875 110_1101b 0.1875 * 000_1110b 1.3750 010_1110b 0.9750 100_1110b 0.5750 110_1110b 0.1750 * 000_1111b 1.3625 010_1111b 0.9625 100_1111b 0.5625 110_1111b 0.1625 * 001_0000b 1.3500 011_0000b 0.9500 101_0000b 0.5500 111_0000b 0.1500 * 001_0001b 1.3375 011_0001b 0.9375 101_0001b 0.5375 111_0001b 0.1375 * 001_0010b 1.3250 011_0010b 0.9250 101_0010b 0.5250 111_0010b 0.1250 * 001_0011b 1.3125 011_0011b 0.9125 101_0011b 0.5125 111_0011b 0.1125 * 001_0100b 1.3000 011_0100b 0.9000 101_0100b 0.5000 111_0100b 0.1000 * 001_0101b 1.2875 011_0101b 0.8875 101_0101b 0.4875 * 111_0101b 0.0875 * 001_0110b 1.2750 011_0110b 0.8750 101_0110b 0.4750 * 111_0110b 0.0750 * 001_0111b 1.2625 011_0111b 0.8625 101_0111b 0.4625 * 111_0111b 0.0625 * 001_1000b 1.2500 011_1000b 0.8500 101_1000b 0.4500 * 111_1000b 0.0500 * 001_1001b 1.2375 011_1001b 0.8375 101_1001b 0.4375 * 111_1001b 0.0375 * 001_1010b 1.2250 011_1010b 0.8250 101_1010b 0.4250 * 111_1010b 0.0250 * 001_1011b 1.2125 011_1011b 0.8125 101_1011b 0.4125 * 111_1011b 0.0125 * 001_1100b 1.2000 011_1100b 0.8000 101_1100b 0.4000 * 111_1100b off 001_1101b 1.1875 011_1101b 0.7875 101_1101b 0.3875 * 111_1101b off 001_1110b 1.1750 011_1110b 0.7750 101_1110b 0.3750 * 111_1110b off 001_1111b 1.1625 011_1111b 0.7625 101_1111b 0.3625 * 111_1111b off note: * indicates a vid not required for amd family 10h processors.
ISL6267 19 january 31, 2011 fn7801.0 svi bus protocol the amd processor bus protocol is compliant with smbus send byte protocol for vid transactions (see figure 14). during a send byte transaction, the proce ssor sends the start sequence followed by the slave address of the vr for which the vid command applies. the address byte must be configured according to table 3. the processor then sends the write bit. after the write bit, if the ISL6267 receives a valid address byte, it sends the acknowledge bit. the processor then sends the psi-l bit and vid bits during the data phase. the serial vid 8-bit data field encoding is outlined in ta ble 4. if ISL6267 receives a valid 8-bit code during the data phase, it sends the acknowledge bit. finally, the processor sends the stop sequence. after the ISL6267 has detected the stop, it can then proceed with the vid-on-the-fly transition. operation after the start-up sequence, th e ISL6267 begins regulating the core and northbridge output voltages to the pre-pwrok metal vid programmed. the controller monitors svi commands to determine when to enter power-saving mode, implement dynamic vid changes, and shut down individual outputs. vr offset programming a positive or negative offset is programmed for the core vr using a resistor to ground from the prog1 pin and the northbridge in a similar manner from the prog2 pin. table 5 provides the resistor value to select the desired output voltage offset voltage regulation and load line implementation after the start sequence, the isl6 267 regulates the output voltage to the value set by the vid information, per table 2. the ISL6267 controls the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.55v. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. table 3. svi send byte address description bits description 6:4 always 110b 3 reserved by amd for future use 2 vdd1; if set, then the following data byte contains the vid for vdd1 [note: the ISL6267 does not support vdd1] 1 vdd0; if set, then the following data byte contains the vid for vid0 0 vddnb; if set then the following data byte contains the vid for vidnb table 4. serial vid 8-bit data field encoding bits description 7psi_l: =0 means the processor is at an optimal load for the regulators to enter power-saving mode =1 means the processor is not at an optimal load for the regulators to enter power-saving mode 6:0 svid[6:0] as defined in table 2. figure 14. send byte example 6 54 32 10 5 3 2 1 0 4 7 slave address phase svd data phase svc s t a r t w r i t e a c k s t o p a c k p s i _ l svid 6 see table 3 table 5. progx pin resistor value resistor value [ ] prog1 v core offset [mv] prog1 vnb offset [mv] 05050 590 43.75 43.75 1100 37.50 37.50 1690 31.25 31.25 2260 25.00 25.00 3160 18.75 18.75 4320 12.50 12.50 5620 6.25 6.25 6650 0.00 0.00 7870 -6.25 -6.25 9530 -12.50 -12.50 11500 -18.75 -18.75 14000 -25.00 -25.00 16500 -31.25 -31.25 18700 -37.50 -37.50 open -43.75 -43.75
ISL6267 20 january 31, 2011 fn7801.0 as the load current increases from zero, the output voltage droops from the vid table value by an amount proportional to the load current, to achieve the load line. the ISL6267 can sense the inductor current through the intrin sic dc resistance (dcr) of the inductors, as shown in figures 15 and 16, or through resistors in series with the inductors as shown in figure 17. in both methods, capacitor c n voltage represents the inductor total currents. a droop amplifier converts c n voltage into an internal current source with the gain set by resistor r i . the current source is used for load line implementation, current monitoring and overcurrent protection. figure 15 shows the load-line implementation. the ISL6267 drives a current source (i droop ) out of the fb pin, as described by equation 1. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding, thus sustaining the load-line accuracy with reduced cost. i droop flows through resistor r droop and creates a voltage drop as shown in equation 2. v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can change the load line slope. since i droop also sets the overcurrent protection level, it is recommended to first scale i droop based on ocp requirement, then select an appropriate r droop value to obtain the desired load line slope. differential sensing figure 15 also shows the differential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity ga in differential amplifier senses the vss sense voltage and adds it to the dac output. the error amplifier regulates the inverting and non-inverting input voltages to be equal as shown in equation 3: rewriting equation 3 and subs tituting equation 2 gives equation 4 is the exact equation required for load-line implementation. the vcc sense and vss sense signals come from the processor die. the feedback is, open circuit in the absence of the processor. as figure 15 shows, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and to add another ?catch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ~100 , provide voltage feedback if the system is powered up without a processor installed. phase current balancing the ISL6267 monitors individual phase average current by monitoring the isen1, isen2, and isen3 voltages. figure 16 shows the current balancing circuit recommended for ISL6267. each phase node voltage is averaged by a low-pass filter consisting of r isen and c isen , and is presented to the corresponding isen pin. r isen should be routed to the inductor phase-node pad in order to eliminate the effect of phase node parasitic pcb dcr. equations 5 through 7 give the isen pin voltages: where r dcr1 , r dcr2 and r dcr3 are inductor dcr; r pcb1 , r pcb2 and r pcb3 are parasitic pcb dcr between the inductor output side pad and the output voltage rail; and i l1 , i l2 and i l3 are inductor average currents. figure 15. differential sensing and load line implementation x 1 e/a dac vid<0:7> rdroop idroop vdac vdroop fb comp vcc sense vss sense vids rtn vss internal to ic ?catch? resistor ?catch? resistor vr local vo + - +- + + - i droop 2xv cn r i ---------------- = (eq. 1) v droop r droop i droop = (eq. 2) vcc sense v + droop v dac vss sense + = (eq. 3) vcc sense vss sense ? v dac r droop i droop ? = (eq. 4) figure 16. current balancing circuit internal to ic v o isen3 l3 r isen c isen isen2 r isen c isen isen1 r isen c isen l2 l1 r dcr3 r dcr2 r dcr1 phase3 phase2 phase1 i l3 i l2 i l1 r pcb3 r pcb2 r pcb1 internal v isen1 r dcr1 r pcb1 + () i l1 = (eq. 5) v isen2 r dcr2 r pcb2 + () i l2 = (eq. 6) v isen3 r dcr3 r pcb3 + () i l3 = (eq. 7)
ISL6267 21 january 31, 2011 fn7801.0 the ISL6267 will adjusts the phase pulse-width relative to the other phases to make v isen1 =v isen2 =v isen3 , thus to achieve i l1 =i l2 =i l3 , when r dcr1 =r dcr2 =r dcr3 and r pcb1 =r pcb2 =r pcb3 . using the same components for l1, l2 and l3 provides a good match of r dcr1 , r dcr2 and r dcr3 . board layout determines r pcb1 , r pcb2 and r pcb3 . it is recommended to have symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that r pcb1 =r pcb2 =r pcb3 . sometimes, it is difficult to implement symmetrical layout. for the circuit shown in figure 16, asymmetric layout causes different r pcb1 , r pcb2 and r pcb3 values, thus creating a current imbalance. figure 17 shows a differential sensing current balancing circuit recommended for ISL6267. the current sensing traces should be routed to the inductor pads so they only pick up the inductor dcr voltage. each isen pin sees the average voltage of three sources: its own, phase inductor phase-node pad, and the other two phases inductor output side pads. equations 8 through 10 give the isen pin voltages: the ISL6267 will make v isen1 = v isen2 = v isen3 as shown in equations 11 and 12: rewriting equation 11 gives equation 13: rewriting equation 12 gives equation 14: combining equations 13 and 14 gives: therefore: current balancing (i l1 =i l2 =i l3 ) is achieved when r dcr1 =r dcr2 =r dcr3 . r pcb1 , r pcb2 and r pcb3 do not have any effect. since the slave ripple capacitor voltages mimic the inductor currents, the r 3 ? modulator can naturally achieve excellent current balancing during steady state and dynamic operations. figure 18 shows the current balancing performance of the evaluation board with load transi ent of 12a/51a at different rep rates. the inductor currents follow the load current dynamic change with the output capacitors supplying the difference. the inductor currents can track th e load current well at a low repetition rate, but cannot keep up when the repetition rate gets into the hundred-khz range, where it is out of the control loop bandwidth. the controller achieves excellent current balancing in all cases installed. ccm switching frequency the r fset resistor between the comp and the vw pins sets the vw windows size and therefore sets the switching frequency. when the ISL6267 is in continuo us conduction mode (ccm), the switching frequency is not absolutely constant due to the nature of the r 3 ? modulator. as explained in the ?multiphase r3? modulator? on page 14, the effective switching frequency increases during load insertio n and decreases during load release to achieve fast response. thus, the switching frequency is relatively constant at steady state. variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. the variation is usually less than 15% and does not have any significant effect on output voltage ripple magnitude. equation 17 gives an estimate of the frequency- setting resistor (r fset ) value. a value of 8k r fset gives approximately 300khz switching frequency. lower resistance gives higher switching frequency. figure 17. differential-se nsing current balancing circuit internal to ic v o isen3 l3 r isen cisen isen2 r isen c isen isen1 r isen c isen l2 l1 r dcr3 r dcr2 r dcr1 phase3 phase2 phase1 i l3 i l2 i l1 r pcb3 r pcb2 r pcb1 r isen r isen r isen r isen r isen r isen v3p v 3n v2p v 2n v1p v 1n v isen1 v 1p v 2n v 3n ++ = (eq. 8) v isen2 v 1n v 2p v 3n ++ = (eq. 9) v isen3 v 1n v 2n v 3p ++ = (eq. 10) v 1p v 2n v 3n ++ v 1n v 2p v 3n ++ = (eq. 11) v 1n v 2p v 3n ++ v 1n v 2n v 3p ++ = (eq. 12) v 1p v 1n ? v 2p v 2n ? = (eq. 13) v 2p v 2n ? v 3p v 3n ? = (eq. 14) v 1p v 1n ? v 2p v 2n ? v 3p v 3n ? == (eq. 15) r dcr1 i l1 r dcr2 i l2 r dcr3 i l3 == (eq. 16) r fset k () period s () 0.29 ? () 2.65 = (eq. 17)
ISL6267 22 january 31, 2011 fn7801.0 modes of operation the core vr can be configured for 3, 2- or 1-phase operation. table 6 shows core vr configur ations and operational modes, programmed by the pwm3 and isen2 pin status and the ps command. for 2-phase configuration, tie the pwm3 pin to 5v. in this configuration, phases 1 and 2 are active. for 1-phase configuration, tie the pwm3 pin an d the isen2 pin to 5v. in this configuration, only phase-1 is active and the controller operates in de mode and the psi_l input is ignored. in 3-phase configuratio n, core vr operates in 3-phase ccm, with psi_l high. it enters 1-phase de mode when psi_l is low, dropping phases 3 and 2, and reduces the overcurrent and the way-overcurrent protection levels to one-third of the initial values. in 2-phase configuratio n, core vr operates in 2-phase ccm with psi_l high. it enters 1-phase de mode with psi_l low, by dropping phase 2 and reduces the overcurrent and the way-overcurrent protection levels to one-half of the initial values. in 1-phase configuration, the core vr operates in 1-phase de and ignores the psi_l input. if a resist or is placed from comp pin to gnd with a value less than 150k , then the core vr operates in 1-phase ccm with psi_l high and enters 1-phase de mode when psi_l is low. a resistor value of 100k is recommended. ISL6267 northbridge (nb) vr can be configured for 2- or 1-phase operation. table 7 shows the northbridge vr configurations and operational modes, which are programmed by the isen2 pin status and the psi_l command. for 1-phase configuration, tie the isen2_nb pin to 5v. in 1-phase configuration, the northbridge vr operates in 1-phase de and ignores the psi_l input. if a resistor is placed from comp_nb pin to gnd with a value less than 150k , then the northbridge vr operates in 1- phase ccm with psi_l high and enters 1-phase de mode when psi_l is low. a resistor value of 100k is recommended. the northbridge vr can be disabled completely by tying isumn_nb to 5v. figure 18. current bala ncing during dynamic operation. ch1: i l1 , ch2: i load , ch3: i l2 , ch4: i l3 rep rate = 10khz rep rate = 25khz rep rate = 50khz rep rate = 100khz rep rate = 200khz table 6. core vr modes of operation pwm3 isen2 config. psl_l mode ocp threshold (a) to external driver to power stage 3-phase cpu vr config. 1 3-phase ccm 60 0 1-phase de 20 tied to 5v 2-phase cpu vr config. 1 2-phase ccm 60 0 1-phase de 30 tied to 5v 1-phase cpu vr config. x 1-phase de 60 table 7. northbridge vr modes of operation isen2_nb config. psl_l mode ocp threshold to power stage 2-phase nb vr config. 12-phase ccm 60ua 0 1-phase de 30ua tied to 5v 1-phase nb vr config. x 1-phase de 60ua
ISL6267 23 january 31, 2011 fn7801.0 dynamic operation core vr and northbridge vr be have the same during dynamic operation. the controller responds to vid-on-the-fly changes by slewing to the new voltage at the fixed 7.5mv/s slew rate. during negative vid transitions, the output voltage decays to the lower vid value at the slew rate determined by the load. svi_l low command prompts the controller to enter de mode. overvoltage protection is blanked during vid down transition in de mode until the output voltage is within 60mv of the vid value. during load insertion response, th e fast clock function increases the pwm pulse response speed. the controller monitors the vsen pin voltage and compares it to 100ns-filtered version. when the unfiltered version is 20 mv below the filtered version, the controller knows there is a fast voltage dip due to load insertion, and it issues an addi tional master clock signal to deliver a pwm pulse immediately. the r 3 ? modulator intrinsically has voltage feed-forward. the output voltage is insensitive to a fast slew rate input voltage change. protections core vr and northbridge vr both provide overcurrent, current-balance and overvoltage fault protections. the controller also provides over-temperature protection. the following discussion is based on core vr an d also applies to northbridge vr. the controller determines overcurrent protection (ocp) by comparing the average value of the droop current (i droop ) with an internal current source threshold as table 6 shows. it declares ocp when i droop is above the threshold for 120s. for overcurrent conditions abov e 1.5x the ocp level, the pwm outputs immediately shuts off an d pgood goes low to maximize protection. this protection is also referred to as way-overcurrent protection or fast overcurrent protection for short-circuit protections. the controller monitors the isen pin voltages to determine current-balance protection. if the isen pin voltage difference is greater than 9mv for 1ms, the controller will declare a fault and latch off. the controller takes the same ac tions for all of the previously describe fault protections: de-assertion of pgood and turn-off of the high-side and low-side power mosfets. any residual inductor current decays through the mosfet body diodes. the controller declares an overvoltage fault and de-asserts pgood if the output voltage exceeds the vid set value by +250mv. the ISL6267 immediately declares an ov fault, de-asserts pgood, and turn on the low-side power mosfets. the low-side power mosfets remain on until the outp ut voltage is pulled down below the vid set value when all power mosfets are turned off. if the output voltage rises above the vid set value +250mv again, the protection process is repeated . this behavior provides the maximum amount of protection against shorted high-side power mosfets while preventing output ringing below ground. all of the previously described fault conditions can be reset by bringing enable low or by bringing v dd below the por threshold. when enable and v dd return to their high operating levels, a soft-start occurs. table 8 summarizes the fault protections. fb2 function the fb2 function is only availabl e for core vr or northbridge vr in 2-phase configuration. figure 19 shows the fb2 function. a switch (called fb2 switch) turns on to short the fb and the fb2 pins when the controller is in 2-phase mode. capacitors c3.1 and c3.2 are in parallel, serving as part of the compensator. when the controller enters 1-phase mode, the fb2 switch turns off, removing c3.2 and leaving only c3.1 in the compensator. the compensator gain increases with the removal of c3.2. by properly sizing c3.1 and c3.2, the compensator can be optimal for both 2-phase mode and 1-phase mode. when the fb2 switch is off, c3.2 is disconnected from the fb pin. however, the controller still actively drives the fb2 pin voltage to follow the fb pin voltage such that c3.2 voltage always follows c3.1 voltage. when the controlle r turns on the fb2 switch, c3.2 is reconnected to the compensator smoothly. the fb2 function ensures excellent transient response in both 2-phase and 1-phase mode. if the fb2 function is not used, populate c3.1 only. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative, and the amount is the table 8. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm tri-state, pgood latched low enable toggle or vdd toggle phase current unbalance 1ms way-overcurrent (1.5xoc) immediately overvoltage +200mv pgood latched low. actively pulls the output voltage to below vid value, then tri-state. over-temperature 400s n/a r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen controller in 2-phase mode controller in 1-phase mode figure 19. fb2 function
ISL6267 24 january 31, 2011 fn7801.0 mosfet r ds(on) voltage drop, which is proportional to the inductor current. a phase comparator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero crossing point of the inductor current. if the inductor current has not reached zero when the low-side mosfet turns off, it will flow through the low-side mosfet body diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it will flow through the high-side mosfet body diode, causing the phase node to have a spike until it decays to zero. th e controller continues monitoring the phase voltage after turning off the low-side mosfet. to minimize the body diode-related loss, the controller also adjusts the phase comparator threshold vo ltage accordingly in iterative steps such that the low-side mosfet body diode conducts for approximately 40ns. key component selection inductor dcr current-sensing network figure 20 shows the inductor dcr current-sensing network for a 3-phase solution. an inductor current flows through the dcr and creates a voltage drop. each inductor has two resistors in r sum and r o connected to the pads to a ccurately sense the inductor current by sensing the dcr voltage drop. the r sum and r o resistors are connected in a summing network as shown, and feed the total current information to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to temperature compensate the inductor dcr change. the inductor output side pads are electrically shorted in the schematic but have some parasi tic impedance in actual board layout, which is why one cannot simply short them together for the current-sensing summing network. it is recommended to use 1 ~10 r o to create quality signals. since r o value is much smaller than the rest of the current sensing circuit, the following analysis ignores it. the summed inductor current information is presented to the capacitor c n . equations 18 thru 22 describe the frequency domain relationship between inductor total current i o (s) and c n voltage v cn (s): where n is the number of phases. transfer function a cs (s) always has unity gain at dc. the inductor dcr value increases as the wi nding temperature increases, giving higher reading of the inductor dc current. the ntc r ntc value decrease as its temperature decreases. proper selection of r sum , r ntcs , r p and r ntc parameters ensures that v cn represents the inductor total dc current over the temperature range of interest. there are many sets of parameters that can properly temperature- compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltage. it is recommended to have a higher ratio of v cn to the inductor dcr voltage so the droop circuit has a higher signal level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 3.65k , r p =11k , r ntcs = 2.61k and r ntc = 10k (ert-j1vr103j). the ntc network parameters may need to be fine tuned on actual boards. one can apply full load dc current and record the output voltage reading immediately; then record the ou tput voltage reading again when the board has reached the thermal steady state. a good ntc network can limit the output voltag e drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current sensing network parameters to minimize engineering time. v cn (s) also needs to represent real-time i o (s) for the controller to achieve good transient response. transfer function a cs (s) has a pole w sns and a zero w l . one needs to match w l and w sns so a cs (s) is unity gain at all frequencies. by forcing w l equal to w sns and solving for the solution, equation 23 gives cn value. cn r sum r o r ntcs r ntc r p dcr l dcr l r sum r o phase2 phase3 i o dcr l phase1 r o r sum ri i sum+ i sum- vcn + - figure 20. dcr current-sensing network v cn s () r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o s () a cs s () = (eq. 18) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - = (eq. 19) a cs s () 1 s l ------ + 1 s sns ------------ + ---------------------- = (eq. 20) l dcr l ----------- - = (eq. 21) sns 1 r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- c n ------------------------------------------------------ = (eq. 22)
ISL6267 25 january 31, 2011 fn7801.0 for example, given n = 3, r sum = 3.65k , r p = 11k , r ntcs =2.61k , r ntc = 10k , dcr = 0.88m and l = 0.36h, equation 23 gives c n = 0.406f. assuming the compensator design is correct, figure 21 shows the expected load transient response waveforms if c n is correctly selected. when the load current i core has a square change, the output voltage v core also has a square response. if c n value is too large or too small, v cn (s) does not accurately represent real-time i o (s) and worsens the transient response. figure 22 shows the load transient response when c n is too small. v core sags excessively upon load insertion and may create a system failure. figure 23 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there is excessive overshoot if load insertion occurs during this time, which may negatively affect the cpu reliability. figure 24 shows the output voltage ring-back problem during load transient response. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first-order system fashion due to the nature of the current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore, it pulls v o back to the level dictated by i l , causing the ring-back problem. this phenomen on is not observed when the output capacitor has very low esr and esl, as is the case with all ceramic capacitors. figure 25 shows two optional circuits for reduction of the ring-back. c n is the capacitor used to match the inductor time constant. it usually takes the parallel of two (or more) capacitors to get the desired value. figure 25 shows that two capacitors (c n.1 and c n.2 ) are in parallel. resistor r n is an optional component to reduce the v o ring-back. at steady state, c n.1 + c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective capacitance is less because r n increases the impedance of the c n.1 branch. as figure 22 shows, v o tends to dip when c n is too small, and this effect reduces the v o ring-back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. r n value usually is a few ohms. c n.1 , c n.2 and r n values c n l r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- dcr ----------------------------------------------------------- - = (eq. 23) figure 21. desired load transient response waveforms o i v o figure 22. load transient response when c n is too small o i v o figure 23. load transient response when c n is too large o i v o figure 24. output voltage ring-back problem o i v o l i ring back figure 25. optional circuits for ring-back reduction cn.2 rntcs rntc rp ri isum+ isum- rip cip optional vcn cn.1 rn optional
ISL6267 26 january 31, 2011 fn7801.0 should be determined through tuni ng the load transient response waveforms on an actual board. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is 100 . c ip should be determined through tuning the load transient response waveforms on an actual board. the recommended range for c ip is 100pf~2000pf. however, it should be noted that the r ip -c ip branch may distort the i droop waveform. instead of being triangular as the real inductor current, i droop may have sharp spikes, which may adversely affect i droop average value detection and therefore may affect ocp accuracy. user discretion is advised. resistor current-sensing network figure 26 shows the resistor current-sensing network for a 2-phase solution. each inductor has a series current sensing resistor, r sen . r sum and r o are connected to the r sen pads to accurately capture the inductor current information. the r sum and r o resistors are connected to capacitor c n . r sum and c n form a filter for noise attenuatio n. equations 24 thru 26 give the v cn (s) expression. transfer function a rsen (s) always has unity gain at dc. current- sensing resistor r sen value does not have significant variation over-temperature, so there is no need for the ntc network. the recommended values are r sum = 1k and c n = 5600pf. overcurrent protection refer to equation 1 on page 20 and figures 20, 24 and 26; resistor r i sets the droop current, i droop . tables 6 and 7 show the internal ocp threshold. it is recommended to design i droop without using the r comp resistor. for example, the ocp threshold is 60a for 3-phase solution. i droop is designed to be 40.9a at full load, so the ocp trip level is 1.5x of the full load current. for inductor dcr sensing, equation 27 gives the dc relationship of v cn (s) and i o (s): substitution of equation 27 into equation 1 gives equation 28: therefore: substitution of equation 19 and application of the ocp condition in equation 29 gives equation 30: where i omax is the full load current and i droopmax is the corresponding droop current. for example, given n = 3, r sum = 3.65k , r p = 11k , r ntcs = 2.61k , r ntc = 10k , dcr = 0.88m , i omax = 51a and i droopmax = 40.9a. equation 30 gives r i = 606 . for resistor sensing, equation 31 gives the dc relationship of v cn (s) and i o (s). substitution of equation 31 in to equation 1 gives equation 32: therefore: substitution of equation 33 and application of the ocp condition in equation 29 gives equation 34: where i omax is the full load current and i droopmax is the corresponding droop current. for example, given n = 3, r sen =1m , i omax = 51a and i droopmax = 40.9a, equation 34 gives r i = 831 . figure 26. resistor cu rrent-sensing network cn r sum r o dcr l dcr l r sum r o phase2 phase3 i o dcr l phase1 r o r sum ri i sum+ i sum- vcn rsen rsen rsen + - v cn s () r sen n ------------ i o s () a rsen s () = (eq. 24) a rsen s () 1 1 s sns ------------ + ---------------------- = (eq. 25) rsen 1 r sum n -------------- c n --------------------------- = (eq. 26) v cn r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o = (eq. 27) i droop 2 r i ---- - r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - i o = (eq. 28) r i 2r ntcnet dcr i o nr ntcnet r sum n -------------- + ?? ?? i droop ------------------------------------------------------------------------------- - = (eq. 29) r i 2 r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - dcr i omax n r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - r sum n -------------- + ?? ?? ?? i droopmax ------------------------------------------------------------------------------------------------------------------------- = (eq. 30) v cn r sen n ------------ i o = (eq. 31) i droop 2 r i ---- - r sen n ------------ i o = (eq. 32) r i 2r sen i o ni droop --------------------------- = (eq. 33) r i 2r sen i omax ni droopmax -------------------------------------- = (eq. 34)
ISL6267 27 january 31, 2011 fn7801.0 load line slope see figure 15 for load-line implementation. for inductor dcr sensing, substitution of equation 28 into equation 2 gives the load-line slope expression: for resistor sensing, substitution of equation 32 into equation 2 gives the load line slope expression : substitution of equation 29 and rewriting equation 35, or substitution of equation 33 and rewriting equation 36, gives the same result as in equation 37: one can use the full-load condition to calculate r droop . for example, given i omax = 51a, i droopmax = 40.9a and ll = 1.9m , equation 37 gives r droop = 2.37k . it is recommended to start with the r droop value calculated by equation 37 and fine-tune it on the actual board to get accurate load-line slope. one should record the output voltage readings at no load and at full load for load -line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. compensator figure 21 shows the desired load transient response waveforms. figure 27 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (= vid) and output impedance z out (s). if z out (s) is equal to the load-line slope ll, i.e., a constant output impedance, then in the entire frequency range, v o will have a square response when i o has a square change. intersil provides a microsoft excel-based spreadsheet to help design the compensator and the cu rrent sensing network so that vr achieves constant output impedance as a stable system. figure 29 shows a screenshot of the spreadsheet. a vr with active droop function is a dual-loop system consisting of a voltage loop and a droop loop, which is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. figure 28 conceptually shows t1(s) measurement set-up , and figure 29 conceptually shows t2(s) measurement set-up. the vr senses the inductor current, multiplies it by a gain of the load-line slope, adds it on top of the sensed output voltage, and then feeds it to the compensator. t1 is measured af ter the summing node, and t2 is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can actually be measured on an ISL6267 regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s), therefore has a higher impact on system stability. t2(s) is the voltage loop gain with closed droop l oop, thus having a higher impact on output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin and an output impedance equal to or smaller than the load-line slope. current balancing refer to figures 16 through 20 for information on current balancing. the ISL6267 achiev es current balancing through matching the isen pin voltages. r isen and c isen form filters to remove the switching ripple of the phase node voltages. it is ll v droop i o ----------------- - 2r droop r i ---------------------- r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - == (eq. 35) ll v droop i o ----------------- - 2r sen r droop nr i ----------------------------------------- == (eq. 36) r droop i o i droop --------------- - ll = (eq. 37) figure 27. voltage regulator equivalent circuit o i v o vid z out (s) = ll load vr figure 28. loop gain t1 (s) measurement set-up q2 q1 l i o c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer + + + - figure 29. loop gain t2 (s) measurement set-up q2 q1 l i o c o v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer + + + -
ISL6267 28 january 31, 2011 fn7801.0 recommended to use a rather long r isen c isen time constant such that the isen voltages have mini mal ripple and represent the dc current flowing through the inductors. recommended values are r s = 10k and c s = 0.22f. ntc thermal monitors and vr_hot function the ISL6267 features three pins (ntc, ntc_nb, and vr_hot) that allow the ic to monitor board temperature and alert the amd cpu of a thermal issue. figure 30 shows the thermal monitor feature of the ISL6267. an ntc network is connected between the ntc and ntc_nb pins and gnd. the controller drives a 60a current source ou t of the ntc pin and the ntc_nb pin alternatively at 1khz frequency with 50% duty cycle. the pulsed current flows through the respective ntc resistor network on the pins and creates a voltage that is compared to an over-temperature trip threshold. if the voltage on both ntc pins is higher than the over-temperature trip threshold, then vr_hot is pulled up by an external resistor on the pin. as the board temperature rises, the ntc thermistor resistance decreases and the voltage at the ntc pin drops. when the voltage on the ntc pin drops below the over-temperature trip threshold, then vr_hot is pulled low. the vr_hot signal is used to change the cpu operation an d decrease power consumption. with the reduction in power cons umption by the cpu, the board temperature decreases and the nt c thermistor voltage rises. once the over-temperature threshold is tripped and vr_hot is taken low, the over-temperature threshold changes to the reset level. the addition of hysteresis to the over-temperature threshold prevents nuisance trips. once both pin voltages exceed the over-temperature reset thresh old, the pull-down on vr_hot is released. the signal changes state and the cpu resumes normal operation. the over-tempe rature threshold returns to the trip level. selection of the ntc components can vary depending on how the resistor network is configured. th e equivalent resistance at the typical over-temperature threshold voltage of 0.88v, to change the state of vr_hot, is defined in equation 38. the equivalent resistance at the typical reset threshold voltage of 0.92v required to change the state of vr_hot back low, is defined in equation 39. the ntc thermistor value correlates this resistance change to the required temperature hysteresis. a standard 1% resistor is typically needed to meet the ntc pin threshold voltage. for example, a panasonic ntc thermistor with b = 4700 has a resistance ratio of 0.03322 of its nominal value at +105c and 0.03956 of its nominal value at +100c. the required resistance of the ntc is defined in equation 40. the closest, larger thermistor value for b = 4700 is 100k . the ntc thermistor part number is ertj1vv104. at +105c, a 100k ntc resistance drops to (0.03322 x 100k ) = 3.322k . with a 60a current flowing out of the ntc pin, the voltage drop across the resistor is only (3.322k x 60a) = 0.199v. this value is much lower than the threshold voltage of 0.88v. a stan dard resistor, 1% tolerance, added in series with the thermi stor is required to raise the voltage on the pin. the resistance required to meet the trip threshold is calculated in equation 41. the closest, standard 1% tolerance resistor is 11.3k . the ntc thermistor is placed in a hot spot on the board, typically near the upper mosfet of channel 1 of the respective output. the standard resistor is plac ed next to the controller. layout guidelines table 9 shows layout considerations for the ISL6267 controller. refer to the reference designators shown in figure 31. ntc r ntc v ntc - + vr_hot 60a internal to ISL6267 figure 30. circuitry associated with the thermal monitor feature of the ISL6267 r s sw1 ntc_nb r ntc v ntc - + r s sw2 monitor sw1 sw2 r p r +v r p 0.88v 60 a --------------- 14.7k = (eq. 38) 0.92v 60 a --------------- 15.3k = (eq. 39) 15.3k 14.7k ? () 0.03956 0.03322 ? () ------------------------------------------------------- 94.6k = (eq. 40) 0.88v 60 a --------------- 3.322k ? 11.34k = (eq. 41) table 9. layout considerations for the ISL6267 controller ISL6267 symbol layout guidelines bottom pad gnd create analog ground plane underneath the contro ller and the analog signal proc essing components. do not let the power ground plane overlap with the analog ground plane. avoid allowing noisy planes/traces (e.g., phase node) to crossover/overlap the analog plane.
ISL6267 29 january 31, 2011 fn7801.0 1 fb2_nb place the compensator components (r25, r9, r24, c88, c51, c86, and c153) close to the controller. 2fb_nb 3comp_nb 4 vw_nb place the capacitor (c85) across vw, and place comp close to the controller. 5 pgood_nb no special consideration. 6, 7, 8 svd, pwrok, svc use good signal integrity practices. 9 enable no special consideration. 10 pgood no special consideration. 11 vr_hot no special consideration. 12 ntc place the ntc thermistor (r46) close to the th ermal source that is monitored to determine cpu v core thermal throttling. usually it is placed close to core vr phase-1 high-side mosfet. 13 vw place the capacitor (c4) across vw and comp close to the controller. 14 comp place the compensator components (r7, r10, r11, c3 , c6, c11 and c5) in general proximity to the controller. 15 fb 16 fb2 isen3 each isen pin has a capacitor (c isen ) decoupling it to vsumn and then through another capacitor (c vsumn ) to gnd. place cisen capacitors as close as possible to the controller and keep the following loops small: 1. any isen pin to another isen pin 2. any isen pin to gnd the red traces in the following drawing show the loops to be minimized. 17 isen2 18 isen1 19 vsen place the vsen/rtn filter (c12, c13) close to the controller for good decoupling. 20 rtn table 9. layout considerations for the ISL6267 controller (continued) ISL6267 symbol layout guidelines v o isen3 l3 risen isen2 isen1 l2 l1 risen risen phase1 phase2 phase3 ro ro ro gnd cisen cisen cisen cvsumn vsumn
ISL6267 30 january 31, 2011 fn7801.0 21 isumn place the current sensing circuit in general proximity of the controller. place capacitor cn very close to the controller. place the ntc thermistor next to vr1 phase-1 inductor (l 1) so it senses the inductor temperature correctly. each phase of the power stage sends a pair of vsum p and vsumn signals to the controller. run these two signals traces in parallel fashion with decent width (>20mil). important: sense the inductor current by routing the se nsing circuit to the inductor pads. route r63 and r71 to core vr phase-1 side pad of inductor l1. route r88 to the output side pad of inductor l1. route r65 and r72 to core vr phase-2 side pad of inductor l2. route r 90 to the output side pad of inductor l2. if possible, route the traces on a different layer from the inductor pa d layer and use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. the following drawings show the two pr eferred ways of routing current sensing traces. 22 isump 23 vdd a capacitor (c16) decouples it to gnd. place it in close proximity to the controller. 24 vin a capacitor (c17) decouples it to gnd. place it in close proximity to the controller. 25 prog1 no special consideration. 26 boot1 use decent wide trace (>30mil). avoid any sensitive analog signal trace from cros sing over or getting close. 27 ugate1 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing ph ase1 trace to vr1 phase-1 high-side mosfet (q2 and q8) source pins instead of general copper. 28 phase1 29 lgate1 use decent width (>30mil). avoid any sensitive anal og signal trace from crossing over or getting close. 30 pwm3 no special consideration. 31 vccp a capacitor (c22) decouples it to gnd. place it in close proximity to the controller. 32 lgate2 use decent width (>30mil). avoid any sensitive anal og signal trace from crossing over or getting close. 33 phase2 run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing ph ase2 trace to vr1 phase-2 high-side mosfet (q4 and q10) source pins instead of general copper. 34 ugate2 35 boot2 use decent wide trace (>30mil). avoid any sensitive analog signal trace from cros sing over or getting close. 36 pwm2_nb no special consideration. 37 lgate1_nb use decent width (>30mil). avoid any sensitive an alog signal trace from crossing over or getting close. 38 phase1_nb run these two traces in parallel fashion with decent width (>30mil). avoid any sensitive analog signal trace from crossing over or getting close. recommend routing ph ase1g trace to vr2 phase-1 high-side mosfet source pins instead of general copper. 39 ugate1_nb 40 boot1_nb use decent wide trace (>30mil). avoid any sensitive analog signal trace from cros sing over or getting close. 41 prog2 no special consideration. 42 ntc_nb place the ntc thermistor cl ose to the thermal source that is monitored to determine gt v core thermal throttling. usually it is placed close to northbridge vr phase-1 high-side mosfet. 43 isumn_nb place the current sensing circuit in general proximity to the controller. place capacitor cn very close to the controller. place the ntc thermistor next to northbridge vr phase-1 inductor (l1) so it senses the inductor temperature correctly. see isumn and isump pins for layout guidelines of current-sensing trace routing. 44 isump_nb table 9. layout considerations for the ISL6267 controller (continued) ISL6267 symbol layout guidelines inductor current-sensing traces vias inductor current-sensing traces
ISL6267 31 january 31, 2011 fn7801.0 45 rtn_nb place the vsen/rtn filter (c89, c90) in cl ose proximity to the controller for good decoupling. 46 vsen_nb 47 isen2_nb see isen1, isen2 and isen3 pins for layout guidelines of current-balancing circuit trace routing. 48 isen1_nb table 9. layout considerations for the ISL6267 controller (continued) ISL6267 symbol layout guidelines figure 31. portion of ISL6267eva l1z evaluation board schematic
ISL6267 32 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com january 31, 2011 fn7801.0 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL6267 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 1/31/11 fn7801.0 initial release.
ISL6267 33 january 31, 2011 fn7801.0 package outline drawing l48.6x6b 48 lead quad flat no-lead plastic package rev 0, 9/09 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6.00 a b pin 1 index area (4x) 0.15 6 6.00 4.4 37 44x 0.40 4x pin #1 index area 48 6 4 .40 0.15 1 ab 48x 0.45 0.10 24 13 48x 0.20 4 0.10 c m 36 25 12 max 1.00 seating plane base plane 5 c 0 . 2 ref 0 . 00 min. 0 . 05 max. 0.10 c 0.08 c c see detail "x" ( 5. 75 typ ) ( 4. 40 ) ( 48x 0 . 20 ) ( 48x 0 . 65 ) ( 44 x 0 . 40 ) 0.05 m c

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